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When sparse computation makes communication dense

The official NVIDIA Technical Blog published this post on July 21, 2026. It uses a DeepSeek-V3 671B pre-training run to make a broader systems argument: mixture-of-experts models save arithmetic by activating only part of the network for each token, but that efficiency moves the limiting resource toward communication.

DeepSeek-V3 illustrates the exchange. The model contains 671 billion parameters but activates roughly 37 billion for a token, giving it the per-token compute cost of a much smaller dense model. The selected experts are distributed across GPUs, however. At every MoE layer, tokens must be dispatched to those experts and their outputs gathered in both the forward and backward passes. This all-to-all collective is not occasional background traffic; it sits directly on the critical path of every layer and every training step.

That distinction changes how a training cluster should be designed. Dense-model scaling often emphasizes accelerator FLOPs, memory capacity, and periodic gradient synchronization. Large MoE training also depends on whether fine-grained token traffic can move with low and predictable latency. A small delay repeated at every layer eventually stops fitting underneath useful computation. At that point, adding GPUs can increase the amount of communication without increasing the number of training tokens completed per second.

The post separates the problem into two communication domains. Tensor-parallel reductions and expert all-to-all traffic are frequent and latency-sensitive, so they belong inside a tightly coupled scale-up domain. Gradient synchronization across racks is less frequent and can be overlapped with compute, but its tail latency must remain bounded: one slow path can still determine the duration of the step. The useful performance metric is therefore delivered work, not the accelerator’s theoretical peak.

Treating the rack as one communication machine

NVIDIA’s GB300 NVL72 design makes a rack of 72 Blackwell Ultra GPUs the scale-up unit. Fifth-generation NVLink gives each GPU 1.8 TB/s of bandwidth and the rack 130 TB/s of non-blocking all-to-all bandwidth, with every GPU able to reach every other GPU in a single hop. More important than the headline bandwidth is the programming and transport model: the fabric is lossless and memory-semantic, so a GPU can read or write a peer’s HBM through native load and store operations instead of sending a software-managed message through a conventional NIC path.

This architecture matches the shape of MoE traffic. Per-layer expert dispatch and tensor-parallel collectives remain within the fast rack-scale fabric. When the job grows beyond one rack, ConnectX-8 SuperNICs provide 800 Gb/s per GPU over Quantum-X800 InfiniBand or Spectrum-X Ethernet. The objective is to finish cross-rack gradient traffic inside the compute window while keeping the latency-sensitive token exchange local.

The rest of the platform is arranged to keep infrastructure work away from that path. BlueField data processing units handle virtual networking, storage access, security, telemetry, and lifecycle operations in an isolated processing domain, reducing host-CPU interference. Megatron Core is tuned directly for the platform, while NVIDIA also contributes optimizations to the open TorchTitan and JAX training stacks. The important mechanism is co-design across topology, transport, runtime, and framework—not merely installing faster GPUs in an otherwise unchanged cluster.

Software maturity compounds the hardware gain

Using Megatron Core on 256 GB300 GPUs, NVIDIA reports 1,648 delivered TFLOPs per GPU while pre-training DeepSeek-V3 671B. An earlier GB200 result reached 606 TFLOPs per GPU. The roughly threefold difference is striking, but the comparison combines a new hardware generation with a newer software stack, so it should not be read as a silicon-only improvement.

The same-hardware measurements make the software contribution clearer. On GB300 NVL72, delivered performance rose from 1,088 to 1,648 TFLOPs per GPU over six months, a 1.5-fold increase without changing the machines. NVIDIA reports a similar maturation curve for community frameworks: successive TorchTitan optimizations produced about a sixfold gain on the workload, while JAX improved nearly tenfold over six months and reached 1,025 TFLOPs per GPU at 256-GPU scale.

These curves expose an often-hidden fact about new accelerators. Initial benchmark numbers describe a point in a software stack’s development, not a fixed property of the hardware. Compiler scheduling, kernel fusion, collective implementations, parallelism strategy, and topology awareness can leave large amounts of performance unrealized at launch. Framework choice also changes how quickly those gains become available to a team: a vendor-tuned stack may lead first, while open frameworks narrow the gap as optimizations land upstream.

The scale-out results test whether those local gains survive a larger system. When the DeepSeek-V3 run expands from 256 to 1,024 GPUs, Megatron Core retains 98.5 percent of its per-GPU throughput; TorchTitan and JAX each retain about 97 percent. In other words, four times as many GPUs produce close to four times the aggregate throughput instead of losing a large fraction to communication. NVIDIA attributes that efficiency to keeping per-layer traffic inside the scale-up domain and hiding the lighter cross-rack gradient traffic behind compute.

What the record does—and does not—establish

The results are evidence that a communication-centered architecture can keep a very large sparse model scaling efficiently. They do not by themselves establish the best end-to-end training economics. The post reports NVIDIA-run results for one model family and platform, expressed primarily in delivered TFLOPs. It does not provide a neutral comparison of total training time, energy, acquisition cost, fault recovery, or convergence quality across alternative systems. The large framework-improvement factors also start from early software baselines, which makes them useful as maturation stories but less useful as steady-state product comparisons.

Those limitations do not weaken the central engineering lesson. Sparse activation removes computation only by introducing routing and data movement. The resulting system must be optimized around the collective pattern actually on the critical path: place expert traffic within a high-bandwidth domain, make topology visible to the training software, overlap the collectives that can be hidden, isolate infrastructure processing, and measure scaling efficiency rather than quoting peak FLOPs.

The broader takeaway is that frontier training performance is increasingly an emergent property of the whole stack. Model architecture determines communication; communication determines topology; topology shapes the parallelism strategy; and framework maturity decides how much of the hardware can be delivered to the workload. NVIDIA’s record is most useful not as a single number, but as a demonstration that when MoE models make arithmetic sparse, the surrounding system has to make communication behave as though the rack were one machine.